U.S. Pat. No. 6,501,169 (Aoki et al.) discloses a semiconductor device of a CSP (Chip Scale Package) structure.
U.S. Patent Application Publication No. 20070034405 A1 (Brown) addresses the problem of increasing routing efficiency in context of area array packages (BGAs and CGAs) mounted on printed circuit boards (PCB or circuit card). The technology should be capable of providing all the necessary escape routes from the electronic device and at the same time be cost effective. One of the mentioned cost factors is the overall layer count. On the other hand, higher pin counts and finer pitches require improved routing solutions. The Brown U.S. publication provides a PCB and BGA package using rows/columns of micro-vias to create printed wiring boards (PWB) routing channels in a BGA that couple with BGA interconnect vias. Simple patterns, created through the reconfiguration of printed circuit board interconnect structures, permit an increase in escape densities that in turn enable the routing of area array devices in fewer layers. The disclosed patterns provide a combination of through and micro-via interconnects to achieve a better routing capability.
A high wireability microvia substrate is discloses also in U.S. Patent Application Publication No. 20060012054 A1 (Memis).
As to the manufacture of the packages itself, U.S. Patent Application Publication No. 20090053858 A1 (Ko et al.), for instance, discloses using a redistribution substrate for providing the escape routes from the component. The solution of the Ko et al. U.S. publication can effectively provide the redistribution lines in case the number of component lands is not excessive.
U.S. Patent Application Publication No. 20080136003 A1 (Pendse) discloses a multi-layer semiconductor package comprising a base substrate with a semiconductor die mounted on a top side of the base substrate. The package further comprises an interposer substrate mounted on top of the die for mounting of additional electronic components.
U.S. Patent Application Publication No. 20040251531 A1 (Yang et al.) discloses a stack type flip-chip package including a substrate board, a first chip, a second chip, a packaging material and a heat sink. The substrate board has bump contacts and line contacts thereon, wherein the bump contacts connect with the bonding pads on the active surface of the first chip via bumps. The back surface of the first chip has a redistribution circuit thereon including bump pads and line pads exposed by a passivation layer, wherein the bump pads connect with the bonding pads of the second chip via bumps, and the line pads are connected to the line contacts via conductive wires. The package further comprises an interposer substrate mounted on top of the die for mounting of additional electronic components.
U.S. Patent Application Publication No. 20080196930 A1 (Tuominen et al.) discloses a multi-layer circuit board with an embedded component. In an embodiment, the component can be connected optionally to either or both of two individual conductor pattern layers via electrical contacts manufactured by growing conductor material in respective contact openings. Ability to make contacts to either or both of the two wiring layers provides an opportunity for the flexible planning of the contacts of the components, and for the efficient use of space in the circuit-board structure.
JP 2001332866 A (MATSUSHITA ELECTRIC) discloses that an additional wiring pattern is made on a semiconductor component by means of semiconductor manufacturing processes. This additional wiring pattern is made on a wafer level before dicing the wafer. The additional wiring pattern can be connected to the conductors of an electronic module by means of conductive glue or solder.
Thus, the background art contains several different solutions that seek to provide high routing efficiency with an affordable price of the product. Despite these attempts, there remains need to seek further techniques with potentially improved properties in view of routing efficiency and price, in particular when it is aimed to increase the number of contacts of the components and narrow the pitch between the contact lands or bumps on the component.